LDLL16ENTR datasheet(99/102 Pages) STMICROELECTRONICS

99 / 102 page

List of tables

Table 1.

Pin list description ................................................................... 6

Table 2.

Minimum channel drop-out voltage at maximum current vs TJ ..................................... 9

Table 3.

Output channel mapping to DIN ......................................................... 14

Table 4.

Output channel in fail-safe/stand-alone mode ............................................... 14

Table 5.

PWM frequency range ............................................................... 15

Table 6.

PWM phase shift (in consumer mode) .................................................... 18

Table 7.

Diagnostic blanking time configuration .................................................... 20

Table 8.

Fault reaction mode configuration ....................................................... 21

Table 9.

LED short circuit threshold - group ....................................................... 23

Table 10.

Wake up pattern (WUP) frame .......................................................... 38

Table 11.

Synchronization frame ............................................................... 38

Table 12.

Unicast frame data - operating code and register address ....................................... 40

Table 13.

Unicast frame data - registers access mode ................................................ 40

Table 14.

Global status byte .................................................................. 42

Table 15.

Global status byte field description ....................................................... 42

Table 16.

Unicast CAN FD frame - FTP read ....................................................... 44

Table 17.

Unicast CAN FD frame - FTP write....................................................... 45

Table 18.

RAM memory map .................................................................. 47

Table 19.

Channel PWM duty cycle 0x01h field description ............................................. 49

Table 20.

Channel PWM duty cycle 0x02h field description ............................................. 49

Table 21.

Channel PWM duty cycle 0x03h field description ............................................. 50

Table 22.

Channel PWM duty cycle 0x04h field description ............................................. 51

Table 23.

Channel PWM duty cycle 0x05h field description ............................................. 52

Table 24.

Channel current setting 0x0Ah field description .............................................. 53

Table 25.

Channel current setting 0x0Bh field description .............................................. 53

Table 26.

Channel current setting 0x0Ch field description .............................................. 54

Table 27.

Channel current setting 0x0Dh field description .............................................. 55

Table 28.

Channel mapping on DIN field description .................................................. 56

Table 29.

Device configuration #1 field description ................................................... 57

Table 30.

Device configuration #2 field description ................................................... 59

Table 31.

Device configuration #3 field description ................................................... 60

Table 32.

Dithering......................................................................... 61

Table 33.

Device configuration #4 field description ................................................... 62

Table 34.

State transition bits ................................................................. 62

Table 35.

Watchdog field description ............................................................ 63

Table 36.

Position and chain identifier for responder IDx field description ................................... 64

Table 37.

Channel output on-state voltage 0x1Fh field description ........................................ 65

Table 38.

Channel output on-state voltage 0x20h field description ........................................ 66

Table 39.

Channel output on-state voltage 0x21h field description ........................................ 66

Table 40.

Channel output on-state voltage 0x22h field description ........................................ 67

Table 41.

Channel output on-state voltage 0x22h field description ........................................ 69

Table 42.

Channel short circuit status field description ................................................ 70

Table 43.

Channel open-load status field description ................................................. 71

Table 44.

Channel short to VPRE_REG_X STATUS field description ...................................... 72

Table 45.

Channel VLEDON ADC status refresh field description ......................................... 73

Table 46.

Device status #1 field description ........................................................ 74

Table 47.

Device status #2 field description ........................................................ 74

Table 48.

Device status #3 field description ........................................................ 75

Table 49.

FTP status #1 field description.......................................................... 77

Table 50.

FTP status #2 field description.......................................................... 78

Table 51.

Row 0........................................................................... 79

Table 52.

Row 1........................................................................... 79

Table 53.

Row 2........................................................................... 79

LDLL16EN

List of tables

DS14111 - Rev 5

page 99/102

LDLL16ENTR Datasheet(PDF) 99 Page - STMicroelectronics

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