LDLL16ENTR datasheet(13/102 Pages) STMICROELECTRONICS

13 / 102 page

•

V3V3 > V3V3_POR _H

•

Reset of control register to default values according to the shadow register setting

•

CAN FD light compatible interface inactive

The device leaves automatically reset mode and enters fail-safe/stand-alone mode after 400 ns (typical).

4.1.4

Fail-safe/Stand-alone mode

The device enters fail-safe/stand-alone mode automatically 400 ns (typical) after reset mode.

Fail-safe/stand-alone mode characteristics are:

•

Device operates according to FTP setting and direct input

•

CAN FD light compatible interface wait for communication from the commander

Note:

Control registers can be written but are not active.

When the device leaves this mode, it can enter standby or normal/bus mode. If the device receives the two

following frames:

•

The first frame reads and clears the WD_FAIL bit (bit <15>, Device status register #3)

•

The second frame (not necessarily directly consecutive to the first frame) sets BUSMODE = 1 and

GOSTBY = 0 (bit <0-1>, Device configuration register #4)

The device enters in bus mode.

Note:

If WD_FAIL read and clear operation is not performed (and in case of WD_FAIL = 1) device state remains in fail-

safe but control register is reset to default value.

Upon the condition:

•

DIN low for a time t > tSTDBY AND power on reset delay time (tPOR_DELAY) elapsed AND all channels NOT

set permanently ON in fail-safe (all FS_OUTx_EN bits = [0])

The device enters standby mode.

Upon the condition:

•

V3V3 < V3V3_POR_L

The device enters in reset transition mode:

•

RAM content is reloaded with shadow register content

•

Device remains in fail-safe state with GSB.RSTB = 1, to inform the user any potential write operations

already performed in fail-safe has to be repeated

4.1.5

Normal/Bus mode

The device enters the normal/bus mode if the device receives the following frames:

•

The first frame reads and clears the WD_FAIL bit (bit <15>, Device status register #3)

•

The second frame sets BUSMODE = 1 and GOSTBY = 0 (bit <0-1>, Device configuration register #4)

Note:

If WD_FAIL read and clear operation is not performed (and in case of WD_FAIL = 1) device state remains in fail-

safe but control register is reset to default value.

In this mode the device operates according to its RAM register settings. Direct input access can be enabled/

disabled by a dedicated bit (DIN_EN). In order to maintain the device in normal/bus mode the watchdog toggle bit

has to be refreshed within the watchdog timeout time-frame.

The device leaves normal/bus mode, entering initialization state (to refresh shadow register with FTP

configuration), upon the following conditions:

•

Send to sleep pattern is sent through CAN FD light compatible interface or

•

BUSMODE = 0 and GOSTBY = 1

The device leaves normal/bus mode, entering reset transition state, upon the following conditions:

•

Watchdog failure

•

One frame setting bits (BUSMODE,GOSTBY) = (0,0)

•

One frame setting bits (BUSMODE,GOSTBY) = (1,1)

LDLL16EN

Functional description

DS14111 - Rev 5

page 13/102

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