LDLL16ENTR datasheet(42/102 Pages) STMICROELECTRONICS

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5.7.3

Global status byte (GSB)

Table 14. Global status byte

Bit

Name

GSBN

RSTB

FE2

FE1

The global status byte is described here below.

Table 15. Global status byte field description

Bit # Name

Description

GSBN

Global status bit not

This bit is a NOR combination of the remaining bits of this register:

RSTB nor FE2 nor FE1 nor DE nor GW nor FS

RSTB

Reset bit

The RSTB indicates a device reset. In case this bit is set, all internal RAM control and configuration registers

are set to default and kept in that state until the bit is cleared. Any valid unicast frame requiring GSB in the

response frame clears the reset bit after the responder sent its response frame. No data can be written to RAM

configuration and control registers as long as the reset bit is set. Chain initialization command is executed, but

reset bit not cleared

Not used 0

FE2

Functional error 2

The FE2 indicates the logical OR combination of the following errors:

Any output channel exceeding the LED short circuit threshold (when enabled): SHT_CHx, or

Any output channel in open-load: OL_CHx, or

Any output channel in short circuit with preregulator: OUT_SHT_VPREG_CHx

FE1

Functional error 1

The FE1 reports the following error:

Thermal shutdown: TSD

Device error

The DE indicates the logical OR combination of the following errors:

Short circuit on external NTC: NTC_FAULT, or

Power good threshold not reached: PG_NOT_VP_REG, or

Supply undervoltage fault: VS_UV, or

Open or short circuit fault on DAC reference resistor: RDAC_FAULT

Global warning

The GW is a logical OR combination of warning flags:

Thermal warning:

TW, or

NTC derating active: NTC_DER_ACT

Fail-safe:

The fail-safe bit is set, when the device operates in fail-safe/stand-alone mode

The subsequent data bytes are the data transferred from the responder device with every communication to the

commander.

LDLL16EN

Communication interface

DS14111 - Rev 5

page 42/102

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