LDLL16ENTR datasheet(16/102 Pages) STMICROELECTRONICS

16 / 102 page

The duty cycle is configurable through serial bus (PWM_DUTY_CHx, 8-bit per channel, see the Section 6: FTP

and RAM memory mapping) and the programmed value is stored in the RAM.

The individual duty cycle per channel can be superimposed by a linear 8-bit global dimming PWM_DUTY_ALL

(applicable for outputs mapped to DIN). The resulting duty cycle is the product of

PWM_DUTY_CHx*PWM_DUTY_ALL. Global dimming is not available for function group not mapped to DIN. If

global dimming is not desired, the PWM_DUTY_ALL register has to be programmed with FFh.

Direct input access to outputs can be enabled or disabled for each channel separately in bus/normal mode. If

direct input is enabled (by DIN_EN configuration bit, see the Section 6: FTP and RAM memory mapping), bus

control is applied when DIN = 0. In case of DIN <> 0, the bus control is automatically disabled (after tFILTER

filtering time) and overtaken by DIN: the DIN input control has priority versus bus control. After a timeout higher

than tBUS_CONTROL after the last falling edge on DIN, the bus control is reactivated. The characteristics of the

function group are illustrated in the following flow chart.

LDLL16EN

Functional description

DS14111 - Rev 5

page 16/102

LDLL16ENTR Datasheet(PDF) 16 Page - STMicroelectronics