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LDLL16ENTR Datasheet(PDF) 57 Page - STMicroelectronics |
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LDLL16ENTR Datasheet(HTML) 57 Page - STMicroelectronics |
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57 / 102 page  6.1.4 Device configuration 1 Device configuration register #1 Address 15h Access R/W Data Byte 3 Data Byte 2 Data Byte 1 Data Byte 0 bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - - - - Table 29. Device configuration #1 field description Bit Name Default Description 31-27 - 0h Not used 26 FAULT_REACT_GROUP_0 FTP Fault reaction mode for channels NOT mapped 0: fault on one string, all strings of the same group are turned off 1: fault on one string, no action on other strings of same group 24 FAULT_REACT_GROUP_1 FTP Fault reaction mode for channels mapped to direct input 0: fault on one string, all strings of the same group are turned off 1: Fault on one string, no action on other strings of same group 23-21 PHASE_DEV (Read Only in RAM) FTP PWM phase shift in responder mode: phase shift with regards to SYNC_IO synchronized clock in 15 μs steps: 000: 0 µs 001: 15 µs 010: 30 µs ... 111: 105 µs 20 OUT_DELAY FTP Enable/Disable of gradual output delay: 0: gradual delay disabled 1: gradual delay enabled 19 SYNC_IO_PC FTP Provider/Consumer SYNC_IO: Synchronization of PWM frequency and phase between provider and consumer devices 1: consumer mode selected. SYNC_IO isinput. Clock frequency and phase signal on the SYNC_IO line is used to synchronize own clock 0 (default): provider mode selected. SYNC_IO is output. Device clock frequency with scaler and phase signal is transferred to the SYNC_IO line 18 PWM_SYNC 0 Reset bit for internal PWM counter: 0: PWM counter running 1: PWM counter reset to zero; bit is automatically cleared directly after reset 17-11 - 000h Not used LDLL16EN FTP and RAM memory mapping DS14111 - Rev 5 page 57/102 |
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