LDLL16ENTR datasheet(75/102 Pages) STMICROELECTRONICS

75 / 102 page

6.1.18

Device status 3

Device status register #3

Address

2Eh

Access

Burst read from 2Ch/Read/Read and Clear

Data Byte 3

Data Byte 2

Data Byte 1

Data Byte 0

bit

Table 48. Device status #3 field description

Bit

Name

Default

Description

31-17

Not used

RDAC_FAULT

External DAC reference resistor Fault:

0: No fault on external DAC reference resistor

1: Open or short circuit fault on external DAC reference resistor

WD_FAIL

Watchdog fail:

0: watchdog trigger bit toggled within WD_CONF timeout period - watchdog fail

1: watchdog trigger bit not toggled within WD_CONF timeout period - devices

enters fail-safe/stand-alone

VS_UV

VS undervoltage fault bit:

0: VS > VS_UV

1: VS < VS_UV

13-12

WD_STATUS

Watchdog status bits:

00: 0% < timer status < 24%

01: 24% < timer status < 50%

01: 50% < timer status < 74%

11: timer status > 74%

Not used

DIN_STATUS

Direct input 0 status bit:

0: low logical level at DIN0

1: high logical level at DIN0

NTC_FAULT

NTC fault status bit:

0: no short circuit fault detected on NTC: VNTC > VNTC_SHT

1: short circuit fault detected on NTC: VNTC < VNTC_SHT

NTC_DER_ACT

NTC derating active bit status bit:

0: VNTC > VNTC_TH, no derating active

1: VNTC < VNTC_TH, NTC derating active

OR_OL

OR combination of all channels´ open-load status flags:

0: no open-load is present on any active channel

LDLL16EN

FTP and RAM memory mapping

DS14111 - Rev 5

page 75/102

LDLL16ENTR Datasheet(PDF) 75 Page - STMicroelectronics

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