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LDLL16ENTR Datasheet(PDF) 48 Page - STMicroelectronics |
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LDLL16ENTR Datasheet(HTML) 48 Page - STMicroelectronics |
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48 / 102 page  Address Name Access Content 1Fh VLED_ON_CH0_3 Burst read from address 1Fh 8-bit output on-state voltage channel 0-3 20h VLED_ON_CH4_7 Read 8-bit output on-state voltage channel 4-7 21h VLED_ON_CH8_11 Read 8-bit output on-state voltage channel 8-11 22h VLED_ON_CH12_15 Read 8-bit output on-state voltage channel 12-15 23h Reserved 24h Reserved 25h Reserved 26h Reserved 27h OUT_STATUS_CH0_15 Burst read from address 27h Output status bit channel 0-15 28h SHT_CH0_15 Read/Read &Clear Short circuit detection flag channel 0-15 29h OL_CH0_15 Read/Read &Clear Open-load detection flag channel 0-15 2Ah OUT_SHT_VPREG_CH 0_15 Read/Read &Clear Output shorted to VPREG detection flag channel 0-15 2Bh VLEDON_RFR_CH0_15 Read VLED_ON refresh information bit channel 0-15 2Ch STATUS_1 Burst read from address 2Ch Device status register 1, ADC voltage on VS, VPRE_REG_A, VPRE_REG_B, TJ 2Dh STATUS_2 Read Device status register 2, ADC voltage on NTC, channel lowest output voltage corresponding to VPRE_REG_A and VPRE_REG_B 2Eh STATUS_3 Read/Read &Clear Device status register 3, various status bits 2Fh FTP_STATUS_1 Read Device FTP status 1, read only status of various FTP configuration bits 30h FTP_STATUS_2 Read Device FTP status 2, read only status of FTP configuration fail-safe output permanent enable channel 0-15 34h FTP_PARITY_ERROR Read 16 parity error bits - 1 bit per FTP Row (0 = ok, 1 = error) Reserved 31h-3Fh (except 34h) Reserved for ST testing and trimming LDLL16EN FTP and RAM memory mapping DS14111 - Rev 5 page 48/102 |
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