LDLL16ENTR datasheet(20/102 Pages) STMICROELECTRONICS

20 / 102 page

Figure 12. Output and PWM control concept DIN (Group 1)

DIN= [0]?

Outx off

Yes

PWM_FS_ALL= [0]?

Outx on

Yes

Duty cycle applied on

OUTx

(1) <= PWM_DUTY_ALL

(2) <= PWM_FREQ_DIN

(3) <= duty applied

No delay times applied

Dimming with power line

In the LDLL16EN, PWM dimming through power line is possible by rectifying the VS supply and connecting the

power line to the direct input through resistor divider. A buffer capacitor on VS supply pin has to be able to supply

the device during PWM off state to keep it in operating mode without any reset.

When dimming through power line is performed, PWM frequency is expected in the range of [100÷200 Hz] with

5% minimum duty cycle. The startup time for light function availability is tSTARTUP_PWM_VS.

The tSTARTUP_PWM_VS parameter is the time needed for device startup, from device power up (presence of VS) to

the channel activation.

4.3

Protections and diagnostic

4.3.1

Diagnostic availability and validation - strategy

The LDLL16EN performs a configurable blanking time for the diagnosis, which is applied on the first channel turn

on as well as on each PWM rising edge.

There are 2 configuration bits per each group of channels (DIAG_BLANK_GROUP_X, see the Section 6: FTP

and RAM memory mapping) to set the desired blanking time before validating any fault related to the channel,

either NOT mapped or mapped to DIN.

The possible configuration values are reported in the table below.

Table 7. Diagnostic blanking time configuration

DIAG_BLANK_GROUP_X [1÷0]

tDIAG_BLANK_GROUP_X [µs]

LDLL16EN

Functional description

DS14111 - Rev 5

page 20/102

LDLL16ENTR Datasheet(PDF) 20 Page - STMicroelectronics