LDLL16ENTR datasheet(10/102 Pages) STMICROELECTRONICS

10 / 102 page

In case one or more channels are not enabled, a gradual delay is increased according to the number of channels

turned OFF.

The gradual delay concept is valid in PWM mode as well: in this case, the PWM waveform is shifted and the

gradual delay is applied also when channel is turned OFF.

The output gradual delay feature is valid both for normal/bus mode and fail-safe/stand-alone mode. In this latter

case, direct input (DIN) controls output channels as per FTP setting (DIN_MAP_CHx, 1 bit, see the

Section 6: FTP and RAM memory mapping).

The delay between each output, in DC and PWM mode, is showed in Figure 6 and the Figure 7.

Figure 6. Gradual delay concept - GD active and DC = 100%

Ch 0

tGD = Gradual Delay

n = Channel number

tGD

Ch 1

Ch 2

Ch n

Ch (n-1)

(n-1) * tGD

tGD

Figure 7. Gradual delay concept - GD active and DC = 10%

Ch 0

tGD

Ch 1

Ch 2

PWM_PERIOD

Ch n

Ch (n-1)

PWM_PERIOD

Conditions: Duty_Cycle = 10% & tGD active - behavior valid for any 0% < Duty Cycle < 100%)

(n-1) * tGD

PWM_CNT = 0

PWM_CNT = 255

PWM_CNT = 0

Ch 3

Duty Cycle = 0% & tGD active

Ch 4

2* tGD

PWM_CNT = 255

tGD

LDLL16EN

Linear current sinkers

DS14111 - Rev 5

page 10/102

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