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LDLL16ENTR Datasheet(PDF) 69 Page - STMicroelectronics |
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LDLL16ENTR Datasheet(HTML) 69 Page - STMicroelectronics |
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69 / 102 page ![]() 6.1.11 Channel output status Channel output status register Address 27h Access Burst Read Data Byte 3 Data Byte 2 Data Byte 1 Data Byte 0 bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - OUT_STATUS_CH8-15 OUT_STATUS_CH0-7 Table 41. Channel output on-state voltage 0x22h field description Bit Name Default Description 31-16 - 0 Not used 15 OUT_STATUS_CH15 0 Output status bit 0: channel gate off 1: channel gate on (regardless of the PWM OFF phase) 14 OUT_STATUS_CH14 0 13 OUT_STATUS_CH13 0 12 OUT_STATUS_CH12 0 11 OUT_STATUS_CH11 0 10 OUT_STATUS_CH10 0 9 OUT_STATUS_CH9 0 8 OUT_STATUS_CH8 0 7 OUT_STATUS_CH7 0 6 OUT_STATUS_CH6 0 5 OUT_STATUS_CH5 0 4 OUT_STATUS_CH4 0 3 OUT_STATUS_CH3 0 2 OUT_STATUS_CH2 0 1 OUT_STATUS_CH1 0 0 OUT_STATUS_CH0 0 LDLL16EN FTP and RAM memory mapping DS14111 - Rev 5 page 69/102 |
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