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LDLL16ENTR Datasheet(PDF) 63 Page - STMicroelectronics |
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LDLL16ENTR Datasheet(HTML) 63 Page - STMicroelectronics |
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63 / 102 page ![]() 6.1.8 Watchdog Watchdog register Address 19h Access R/W Data Byte 3 Data Byte 2 Data Byte 1 Data Byte 0 bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - Table 35. Watchdog field description Bit Name Default Description 31-1 - 0 Not used 0 WD_TRIG 0 Watchdog trigger In order to keep device in normal mode/bus mode, this bit must be cyclically toggled within a period configured by WD_CONF bits to refresh the watchdog LDLL16EN FTP and RAM memory mapping DS14111 - Rev 5 page 63/102 |
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