LDLL16ENTR datasheet(14/102 Pages) STMICROELECTRONICS

14 / 102 page

•

V3V3 < V3V3_POR_L

–

RAM content reloaded with shadow register content

–

Device will reach fail-safe state with GSB.RSTB = 1, to inform the application about the reason of this

transition

4.2

Programmable functions

4.2.1

Direct drive and functional configuration

Output channels assignement

The LDLL16EN features 1 direct input pin (DIN).

Each output can be assigned to DIN or to none by 1 dedicated FTP bit (DIN_MAP_CHx, see the Section 6: FTP

and RAM memory mapping) per output channel, as showed in Table 3.

Table 3. Output channel mapping to DIN

DIN_MAP_CHx <0>

Output Channel Status

OUTx NOT mapped (Group 0)

OUTx mapped on DIN (Group 1)

In fail-safe/stand-alone mode, the outputs are always controlled by DIN - according to the assignment defined in

Table 3, except the case when the channel is programmed permanently ON by dedicated FTP bits (FS_OUTx_EN

<0>, see the Section 6: FTP and RAM memory mapping). When this bit is set, the related output channel “x” is

permanently active in fail-safe/stand-alone mode regardless of the DIN, see Table 4.

Table 4. Output channel in fail-safe/stand-alone mode

FS_OUTx_EN <0>

Output channel status

OUTx according to DIN_MAP_CHx <0>

OUTx permanently ON

In case the channel is configured ON in fail-safe/stand-alone mode, a configurable delay of the output activation

after power on reset (tPOR_DELAY) prevents any undesired flashing while configuring the devices and entering

normal/bus mode. In other words, after power on reset, all outputs are kept off till power on reset delay time

elapses to prevent any flashing during the time needed to enter in bus mode operation.

In normal/bus mode, the direct inputs access to outputs can be enabled/disabled for each channel. If enabled

(DIN_EN), bus control is applied when DIN = 0. If DIN is set (DC or PWM) the bus control is automatically

disabled (after elapsing of tFILTER) and overtaken by DIN (the direct inputs have priority versus bus control). Bus

control is re-established upon tBUS_CONTROL elapse after last falling edge on DIN.

For DIN, a read-back information is available. It is forecasted one status bit (DIN_STATUS <0>, see the

Section 6: FTP and RAM memory mapping) to support functional safety.

The LDLL16EN features also 1 VPREG pin to supply the anode of the LED strings through an external pre-

regulator.

LDLL16EN

Functional description

DS14111 - Rev 5

page 14/102

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