LDLL16ENTR datasheet(27/102 Pages) STMICROELECTRONICS

27 / 102 page

4.3.9

Channel output – open-load detection

The LDLL16EN features the open-load (no current regulation) detection, implemented in both bus mode and fail-

safe/stand-alone mode as well.

The open-load detection is masked when the LED supply voltage (VPREG) is below a power good threshold

(VPG_TH_VPREG), which is configurable in the range of (VPG_TH_VPREG_min ÷ VPG_TH_VPREG_max) with a step

equal to VPG_TH_VPREG_step.

There is one status bit (PG_NOT_VPREG, see the Section 6: FTP and RAM memory mapping) to indicate the

selected voltage threshold is reached. If this bit is equal to "1", the desired voltage threshold is not reached and

the diagnostic is disabled; otherwise the threshold is reached and the diagnostic enabled.

After power good threshold is reached, the fault detection starts and the channel is recognized in open-load as

soon as its output voltage, read by ADC, is less than the specified open-load threshold (VOL_TH).

In bus mode, the faulty channel output is latched off and the dedicated fault bit (OL_CHx, see the Section 6: FTP

and RAM memory mapping) is set. The channel output can be restarted and the fault bit will be cleared by

sending a read and clear command to address 29. Selective bitwise read and clear is possible.

In case of fault in fail-safe/stand-alone mode:

•

for the channels configured with FS_OUTx_EN = 0, the output is latched off and it is cleared upon falling

edge of DIN with tDIN_FALL settling time. This means that fault is not cleared during PWM dimming with

PWM off-time shorter than tDIN_FALL time;

•

for the channels configured with FS_OUTx_EN = 1, after elapsing the tAUTORESTART time, the faulty

channel is automatically re-activated and the OL_CHx bit is cleared.

For all (and only) those channels mapped on DIN (DIN_MAP_CHx = 1), the LDLL16EN features the indication of

open-load on FAULT pin.

If the bit OL_EN (see the Section 6: FTP and RAM memory mapping) is equal to "0", the open-load fault detection

is NOT propagated on FAULT bus; whilst if OL_EN = 1, the open-load of the faulty channel is indicated on

associated FAULT bus (pulled low).

Channel open-load event is also reported in the global status byte register, in particular functional error 2 (FE2) bit

is set.

Then, for both mapped and non-mapped channels, according to the status of the fault reaction mode

configuration bit (see Table 8), an automatic deactivation of the complete light function respectively of the faulty

channel only is performed.

The flow chart reported in the Figure 16 shows how the device manages the faulty channel and the channels

corresponding to DIN_MAP_CHx as well as the fault pin handling.

LDLL16EN

Functional description

DS14111 - Rev 5

page 27/102

LDLL16ENTR Datasheet(PDF) 27 Page - STMicroelectronics