LDLL16ENTR datasheet(18/102 Pages) STMICROELECTRONICS

18 / 102 page

The PWM frequency and phase relation of several devices can be synchronized versus each other through the

SYNC_IO pin. There is one dedicated bit (SYNC_IO_PC, see the Section 6: FTP and RAM memory mapping) to

configure the device in Provider [1] or Consumer [0] mode.

In provider mode, the clock frequency with scaler and phase signal is transferred to the SYNC_IO line. In

consumer mode, clock frequency and phase signal on the SYNC_IO line is used to synchronize its own clock.

Consequently the phase relation among several devices can be configured, through FTP only, by PHASE_DEV

bits (3 bits, see the Section 6: FTP and RAM memory mapping).

Table 6. PWM phase shift (in consumer mode)

PHASE_DEV [2÷0]

PWM_PHASE_SHIFT [μs]

bit 2

bit 1

bit 0

105

The internal PWM clock oscillator can be reset by PWM_SYNC bit (see the Section 6: FTP and RAM memory

mapping) in order to start the PWM period at a known phase relation.

Dimming with direct input in fail-safe/stand-alone mode

The LDLL16EN features the channel output PWM dimming through direct input control.

The direct Inputs control the output channels as per FTP setting (see Table 3).

There is 1 configuration bit (PWM_FS_ALL_EN, see the Section 6: FTP and RAM memory mapping) for enabling

internal PWM dimming in stand-alone/fail-safe mode. The PWM signal is deactivated by the related DIN: if DIN =

0, the outputs are off; otherwise the outputs follow the internal PWM signal.

The channel PWM control concept in fail-safe/stand-alone mode is illustrated in the following flow charts.

LDLL16EN

Functional description

DS14111 - Rev 5

page 18/102

LDLL16ENTR Datasheet(PDF) 18 Page - STMicroelectronics