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LDLL16ENTR Datasheet(PDF) 89 Page - STMicroelectronics |
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LDLL16ENTR Datasheet(HTML) 89 Page - STMicroelectronics |
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89 / 102 page ![]() 7.6 Digital timings, digital I/O and ADC characteristics Table 65. Digital timings Symbol Parameter Test conditions Min. Typ. Max. Unit tWD Watchdog timeout period Guaranteed by scan 00(default) 45 50 ms 01 90 100 10 180 200 11 22.5 25 tAUTORESTART Auto-restart time in fail-safe/stand-alone mode Guaranteed by scan 45 50 55 ms tFILTER Filtering time - Time needed for DIN overtaking control on bus mode (after DIN rising edge when DIN_EN set in bus mode) Guaranteed by scan 32 µs tBUS_CONTROL Timeout for bus control re-activation after last falling edge on DIN Guaranteed by scan 10 ms tRX_IDLE Timeout for RX pin in recessive state 550 µs tWAKE_UP Time for a complete wake up (V3V3 > V3V3_POR _H) DIN high for t > tWAKEUP Cap on V3V3 = 1 μF V3V3 > V3V3_POR _H 30 µs tSTDBY Time needed for a transition to standby mode (V3V3 < V3V3_POR_L) DIN low Cap on V3V3 = 1 μF V3V3 < V3V3_POR _L 15 ms tSTARTUP Time needed for the transition from the initialization to standby phase - transition state, VS > VS_POR_H Guaranteed by scan 500 µs tPOR_DELAY Time needed after POR, before configuring the device (all outputs kept off during this time) Guaranteed by scan 00 0 ms 01 25 10 50 11 100 tDIAG_BLANK_GROUP_X Blanking time - for diagnostic validation Guaranteed by scan 00 5 us 01 10 10 15 11 20 tFTP_WR FTP memory writing time Guaranteed by scan 12 ms tDIN_FALL DIN falling edge settling time - for fault clearing Guaranteed by scan 10 ms Note: Digital timings guaranteed by scan. LDLL16EN Electrical characteristics DS14111 - Rev 5 page 89/102 |
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