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LDLL16ENTR Datasheet(PDF) 52 Page - STMicroelectronics |
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LDLL16ENTR Datasheet(HTML) 52 Page - STMicroelectronics |
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52 / 102 page ![]() Channel PWM duty cycle 0x05h register Address 05h Access R/W/BW Data Byte 3 Data Byte 2 Data Byte 1 Data Byte 0 bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PWM_DUTY_CH15 PWM_DUTY_CH14 PWM_DUTY_CH13 PWM_DUTY_CH12 Table 23. Channel PWM duty cycle 0x05h field description Bit Name Default Description 31-24 PWM_DUTY_CH15 00h Exponential individual PWM dimming for channel 15 according to law embedded in the Figure 9 00h: 0% - channel off 01h: 0.10% 7Fh: 3.09% FFh: 100% - channel on in DC 23-16 PWM_DUTY_CH14 00h Exponential individual PWM dimming for channel 14 according to law embedded in the Figure 9 00h: 0% - channel off 01h: 0.10% 7Fh: 3.09% FFh: 100% - channel on in DC 15-8 PWM_DUTY_CH13 00h Exponential individual PWM dimming for channel 13 according to law embedded in the Figure 9 00h: 0% - channel off 01h: 0.10% 7Fh: 3.09% FFh: 100% - channel on in DC 7-0 PWM_DUTY_CH12 00h Exponential individual PWM dimming for channel 12 according to law embedded in the Figure 9 00h: 0% - channel off 01h: 0.10% 7Fh: 3.09% FFh: 100% - channel on in DC LDLL16EN FTP and RAM memory mapping DS14111 - Rev 5 page 52/102 |
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