LDLL16ENTR datasheet(97/102 Pages) STMICROELECTRONICS

97 / 102 page

5.4

Data link layer ................................................................ 33

5.4.1

CAN FD light compatible frame format ....................................... 33

5.4.2

Wake up .............................................................. 34

5.4.3

Error frames ........................................................... 34

5.4.4

Collisions ............................................................. 34

5.4.5

Error handling .......................................................... 34

5.5

Data handling................................................................. 34

5.5.1

Overview.............................................................. 34

5.6

Broadcast frames ............................................................. 36

5.6.1

Frame format .......................................................... 36

5.6.2

Broadcast frame for current setting and PWM duty cycle setting.................... 37

5.6.3

Chain initialization ....................................................... 37

5.6.4

Go to sleep/wake up pattern ............................................... 37

5.6.5

Synchronization frame ................................................... 38

5.7

Unicast frames................................................................ 39

5.7.1

Unicast request frame .................................................... 39

5.7.2

Unicast response frame .................................................. 41

5.7.3

Global status byte (GSB) ................................................. 42

5.7.4

Unicast frame - no data................................................... 43

5.7.5

Unicast frame - single RAM read............................................ 43

5.7.6

Unicast frame - single RAM read and clear .................................... 43

5.7.7

Unicast frame - single ROM read ........................................... 43

5.7.8

Unicast frame - burst read mode RAM register ................................. 43

5.7.9

Unicast frame - single RAM write ........................................... 44

5.7.10

Unicast frame - 3x RAM write .............................................. 44

5.7.11

Unicast CAN FD frame - FTP read .......................................... 44

5.7.12

Unicast CAN FD frame - FTP write .......................................... 45

FTP and RAM memory mapping...................................................46

6.1

Registers description .......................................................... 49

6.1.1

Channel PWM duty cycle ................................................. 49

6.1.2

Channel current setting ................................................... 53

6.1.3

Channel mapping on DIN ................................................. 56

6.1.4

Device configuration 1.................................................... 57

6.1.5

Device configuration 2.................................................... 59

6.1.6

Device configuration 3.................................................... 60

6.1.7

Device configuration 4.................................................... 62

6.1.8

Watchdog ............................................................. 63

6.1.9

Position and chain identifier for responder ID .................................. 64

LDLL16EN

Contents

DS14111 - Rev 5

page 97/102

LDLL16ENTR Datasheet(PDF) 97 Page - STMicroelectronics

LDLL16ENTR Datasheet(HTML) 97 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL