LDLL16ENTR datasheet(101/102 Pages) STMICROELECTRONICS

101 / 102 page

List of figures

Figure 1.

LDLL16EN - simplified application schematic ............................................... 4

Figure 2.

Functional block diagram ............................................................. 5

Figure 3.

Application diagram - example ......................................................... 5

Figure 4.

QFN32L 5x5 connection diagram ....................................................... 6

Figure 5.

Output channels voltage drop in function of the output current and temperature ....................... 9

Figure 6.

Gradual delay concept - GD active and DC = 100%.......................................... 10

Figure 7.

Gradual delay concept - GD active and DC = 10% .......................................... 10

Figure 8.

Device state diagram............................................................... 11

Figure 9.

Duty cycle vs PWM_DUTY_CHx....................................................... 15

Figure 10.

PWM concept for DIN function group.................................................... 17

Figure 11.

PWM control concept fail-safe/stand-alone mode main layer.................................... 19

Figure 12.

Output and PWM control concept DIN (Group 1) ............................................ 20

Figure 13.

Device reaction on fault inputs - flow chart ................................................ 21

Figure 14.

LED short circuit fault management ..................................................... 24

Figure 15.

Short to VPREG fault management...................................................... 26

Figure 16.

Open-load fault management ......................................................... 28

Figure 17.

External CAN transceiver connection - example ............................................ 29

Figure 18.

System overview.................................................................. 30

Figure 19.

Commander block diagram .......................................................... 31

Figure 20.

Responder ECU controller device ...................................................... 32

Figure 21.

CAN FD light compatible communication and protocol controller ................................. 33

Figure 22.

CAN FD Base Frame Format (FBFF).................................................... 33

Figure 23.

Broadcast message flow ............................................................ 36

Figure 24.

Broadcast frame .................................................................. 37

Figure 25.

Broadcast chain initialization ......................................................... 37

Figure 26.

Send-To-Sleep command............................................................ 37

Figure 27.

Synchronization frame .............................................................. 38

Figure 28.

Unicast request communication between commander and responders............................. 39

Figure 29.

Unicast diagnosis request frame ....................................................... 40

Figure 30.

Unicast diagnosis response frame...................................................... 41

Figure 31.

Unicast frame w/o data - commander request and responder answer ............................. 43

Figure 32.

Unicast frame with single RAM read - commander request and responder answer..................... 43

Figure 33.

Unicast frame with single RAM read and clear - commander request and responder answer.............. 43

Figure 34.

Unicast frame with burst read mode RAM register - commander request and responder answer ........... 43

Figure 35.

Unicast frame with single RAM write - commander request and responder answer .................... 44

Figure 36.

Unicast frame with 3x RAM write - commander request and responder answer ....................... 44

Figure 37.

FTP access through CAN bus - programming by physical pin CS ................................ 46

Figure 38.

FTP access through CAN bus - programming by setting SW bit CS ............................... 46

Figure 39.

20 MHz oscillator, dithering - modulation curve ............................................. 61

Figure 40.

NTC circuitry .................................................................... 88

Figure 41.

QFN32L on four-layers PCB.......................................................... 92

Figure 42.

QFN32L 5x5 mm package outline ...................................................... 93

LDLL16EN

List of figures

DS14111 - Rev 5

page 101/102

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