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LDLL16ENTR Datasheet(PDF) 9 Page - STMicroelectronics |
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LDLL16ENTR Datasheet(HTML) 9 Page - STMicroelectronics |
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9 / 102 page ![]() The output channels can be put in parallel to address all those light functions needing higher current than the programmable one. Moreover, the value programmed in the 8-bit DAC per channels group is stored in the RAM and can be reconfigured dynamically in bus/normal mode. 3.3 Channel driver drop-out voltage To guarantee the regulation of the programmed channel current, a minimum output voltage (VOUTx_DROP) across each current generator must be ensured. The Table 2 shows the minimum channel VOUTx_DROP at the boundary of the regulation region (output current is 3% less than the target value, output power MOS already in the triode region). If on one hand a lower than minimum recommended VOUTx_DROP leads to a regulated current lower than the expected one, a too high VOUTx_DROP implies too high power dissipation. To guarantee the current regulation while optimizing the power dissipation on each channel, in the case of maximum current set on one channel and TJ at 125 °C (worst case condition), the minimum output voltage drop (from device OUTx to device GND) is 1 V. In Figure 5. Output channels voltage drop in function of the output current and temperature is shown the generic channel drop-out voltage as function of the channel output current for the 3 main temperature values. Table 2. Minimum channel drop-out voltage at maximum current vs TJ TJ [°C] VOUTx_DROP [V] 125 1 25 0.9 -40 0.875 Figure 5. Output channels voltage drop in function of the output current and temperature 3.4 Channel output gradual delay The LDLL16EN features the output gradual delay, which consists in a gradual turning on of the current generators. In case of driving several outputs simultaneously, the output gradual delay is applied in order to lower the current transients and improve device emissions. This feature can be activated – for all the channels - through one dedicated bit (OUT_DELAY, see the Section 6: FTP and RAM memory mapping). LDLL16EN Linear current sinkers DS14111 - Rev 5 page 9/102 |
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