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LDLL16ENTR Datasheet(PDF) 91 Page - STMicroelectronics |
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LDLL16ENTR Datasheet(HTML) 91 Page - STMicroelectronics |
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91 / 102 page ![]() 7.7 CAN FD light compatible - external shared transceiver interface pins This section describes the electrical characteristics of the interface pins to an external stand-alone shared transceiver: RX input pin, TX and STB output pins. RX input pin Table 68. RX input pin Symbol Parameter Min. Typ. Max. Unit VRXLOW Input voltage dominant level threshold 1.0 1.45 (2.0) V VRXHIGH Input voltage recessive level threshold (1.2) 1.85 2.3 V VRXHYS VRXHIGH-VRXLOW 0.2 0.4 0.6 V RRXPU RX pull up resistor 20 60 110 kΩ CRX RX Input capacitance; guarantee by design 5 pF TX output pin The TX pin is an open drain output, which also actively pulls high (recessive) during data transmission, except for the ACK delimiter. Table 69. TX output pin Symbol Parameter Operating condition Min. Typ. Max. Unit VTXLOW Output voltage dominant level Active mode, ITX = 5.6 mA 0.05 0.2 0.5 V VTXHIGH Output voltage recessive level Active mode, ITX = -2 mA V_IO -0.5 V_IO -0.2 V_IO - 0.05 V tr,TX TX rise time; guarantee by design CL = 50 pF, 30% - 70% VTX 25 ns tf,TX TX fall time; guarantee by design CL = 50 pF, 70% - 30% VTX 25 ns CTX TX utoput capacitance; guarantee by design 5 pF STB output pin The STB pin is a programmable open-drain pin which is either actively pulling high or low. Table 70. STB output pin Symbol Parameter Operating condition Min. Typ. Max. Unit VSTBHIGH Output voltage high level Active mode, ISTB = -2 mA; when actively pulling low V_IO-0.5 V_IO -0.2 V_IO - 0.05 V VSTBLOW Output voltage low level Active mode, ISTB = 2 mA; when actively pulling high 0.05 0.2 0.5 V tr,STB STB rise time (1) CL = 50 pF, 30% - 70% VSTB 250 ns tf,STB STB fall time (1) CL = 50 pF, 70% - 30% VSTB 250 ns 1. Guarantee by design. LDLL16EN Electrical characteristics DS14111 - Rev 5 page 91/102 |
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