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LDLL16ENTR Datasheet(PDF) 59 Page - STMicroelectronics |
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LDLL16ENTR Datasheet(HTML) 59 Page - STMicroelectronics |
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59 / 102 page  6.1.5 Device configuration 2 Device configuration register #2 Address 16h Access R/W Data Byte 3 Data Byte 2 Data Byte 1 Data Byte 0 bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - - - SHT_THR_GROUP_1 - PG_TH_VPREG Table 30. Device configuration #2 field description Bit Name Default Description 31-20 - 0h Not used 19-16 SHT_THR_GROUP_1 FTP Short circuit detection threshold for channels mapped to direct input: Adjustable in 556 mV steps 0h: 0.556 V 1h: 1.112 V 2h: 1.668 V ... Fh: 8.9 V 15-8 - 0h Not used 7-0 PG_TH_VPREG FTP Power good threshold for VPREG adjustable in 78.4 mV steps - from 00h to 32h codes the threshold value is clamped to 4 V: 32h: 4.00 V 7Fh: 10.20 V DFh:17.84 V FFh: 20.40 V LDLL16EN FTP and RAM memory mapping DS14111 - Rev 5 page 59/102 |
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