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XC888LM Datasheet(PDF) 133 Page - Infineon Technologies AG |
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XC888LM Datasheet(HTML) 133 Page - Infineon Technologies AG |
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133 / 144 page  XC886/888CLM Electrical Parameters Data Sheet 126 V0.9, 2006-12 4.3.3 Power-on Reset and PLL Timing Table 50 provides the characteristics of the power-on reset and PLL timing in the XC886/888. Table 47 Power-On Reset and PLL Timing (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions min. typ. max. Pad operating voltage V PAD CC 2.3 – – V On-Chip Oscillator start-up time t OSCST CC – – 500 ns Flash initialization time t FINIT CC – 160 – µs RESET hold time 1) 1) RESET signal has to be active (low) until V DDC has reached 90% of its maximum value (typ. 2.5 V). t RST SR – 500 – µs V DDP rise time (10% – 90%) ≤ 500 µs PLL lock-in in time t LOCK CC – – 200 µs PLL accumulated jitter D P –– 0.7 ns 2) 2) PLL lock at 96 MHz using a 4 MHz external oscillator. The PLL Divider settings are K = 2, N = 48 and P = 1. |
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