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XC888LM Datasheet(PDF) 81 Page - Infineon Technologies AG |
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XC888LM Datasheet(HTML) 81 Page - Infineon Technologies AG |
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81 / 144 page  XC886/888CLM Functional Description Data Sheet 74 V0.9, 2006-12 PLL Mode The system clock is derived from the oscillator clock, multiplied by the N factor, and divided by the P and K factors. Both VCO bypass and PLL bypass must be inactive for this PLL mode. The PLL mode is used during normal system operation. (3.3) System Frequency Selection For the XC886/888, the value of P is fixed to 1. In order to obtain the required fsys, the value of N and K can be selected by bits NDIV and KDIV respectively for different oscillator inputs. The output frequency must always be configured for 96 MHz. Table 24 provides examples on how f sys = 96 MHz can be obtained for the different oscillator sources. Table 24 System frequency ( f sys =96MHz) Oscillator Fosc N P K Fsys On-chip 9.6 MHz 20 1 2 96 MHz External 8 MHz 24 1 2 96 MHz 6 MHz 32 1 2 96 MHz 4 MHz 48 1 2 96 MHz f SYS f OSC N PK × ------------- × = |
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