XC888LM datasheet(95/144 Pages) INFINEON

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XC886/888CLM

Functional Description

Data Sheet

V0.9, 2006-12

3.13.2

Baud Rate Generation using Timer 1

In UART modes 1 and 3 of UART module, Timer 1 can be used for generating the

variable baud rates. In theory, this timer could be used in any of its modes. But in

practice, it should be set into auto-reload mode (Timer 1 mode 2), with its high byte set

to the appropriate value for the required baud rate. The baud rate is determined by the

Timer 1 overflow rate and the value of SMOD as follows:

(3.7)

3.14

Normal Divider Mode (8-bit Auto-reload Timer)

Setting bit FDM in register FDCON to 1 configures the fractional divider to normal divider

mode, while at the same time disables baud rate generation (see Figure 30). Once the

fractional divider is enabled (FDEN = 1), it functions as an 8-bit auto-reload timer (with

no relation to baud rate generation) and counts up from the reload value with each input

clock pulse. Bit field RESULT in register FDRES represents the timer value, while bit

field STEP in register FDSTEP defines the reload value. At each timer overflow, an

overflow flag (FDCON.NDOV) will be set and an interrupt request generated. This gives

an output clock f

MOD that is 1/n of the input clock fDIV, where n is defined by 256 - STEP.

The output frequency in normal divider mode is derived as follows:

(3.8)

Table 31

Deviation Error for UART with Fractional Divider enabled

PCLK

Prescaling Factor

(2BRPRE)

Reload Value

(BR_VALUE + 1)

STEP

Deviation

Error

24 MHz

10 (A

197 (C5

+0.20 %

12 MHz

6 (6

236 (EC

+0.03 %

8MHz

4 (4

236 (EC

+0.03 %

6MHz

3 (3

236 (EC

+0.03 %

Mode 1, 3 baud rate

SMOD

PCLK

256

TH1

–

()

-----------------------------------------------------

MOD

DIV

256

STEP

–

------------------------------

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