XC888LM datasheet(76/144 Pages) INFINEON

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XC886/888CLM

Functional Description

Data Sheet

V0.9, 2006-12

3.7

Reset Control

The XC886/888 has five types of reset: power-on reset, hardware reset, watchdog timer

reset, power-down wake-up reset, and brownout reset.

When the XC886/888 is first powered up, the status of certain pins (see Table 23) must

be defined to ensure proper start operation of the device. At the end of a reset sequence,

the sampled values are latched to select the desired boot option, which cannot be

modified until the next power-on reset or hardware reset. This guarantees stable

conditions during the normal operation of the device.

In order to power up the system properly, the external reset pin RESET must be asserted

until

DDC reaches 0.9*VDDC. The delay of external reset can be realized by an external

capacitor at RESET pin. This capacitor value must be selected so that

RESET reaches

0.4 V, but not before

DDC reaches 0.9* VDDC.

A typical application example is shown in Figure 22. The

DDP capacitor value is 100 nF

while the

DDC capacitor value is 220 nF. The capacitor connected to RESET pin is

100 nF.

Typically, the time taken for

DDC to reach 0.9*VDDC is less than 50 µs once VDDP reaches

2.3V. Hence, based on the condition that 10% to 90%

DDP (slew rate) is less than

500

µs, the RESET pin should be held low for 500 µs typically. See Figure 23.

Figure 22

Reset Circuitry

SSP

DDP

DDC

SSC

3.3 / 5V

RESET

EVR

100nF

220nF

typ.

100nF

XC886/888

30k

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