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XC888LM Datasheet(PDF) 87 Page - Infineon Technologies AG |
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XC888LM Datasheet(HTML) 87 Page - Infineon Technologies AG |
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87 / 144 page ![]() XC886/888CLM Functional Description Data Sheet 80 V0.9, 2006-12 3.10 Watchdog Timer The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and recover from software or hardware failures. The WDT is reset at a regular interval that is predefined by the user. The CPU must service the WDT within this interval to prevent the WDT from causing an XC886/888 system reset. Hence, routine service of the WDT confirms that the system is functioning properly. This ensures that an accidental malfunction of the XC886/888 will be aborted in a user-specified time period. In debug mode, the WDT is default suspended and stops counting. Therefore, there is no need to refresh the WDT during debugging. Features • 16-bit Watchdog Timer • Programmable reload value for upper 8 bits of timer • Programmable window boundary • Selectable input frequency of f PCLK/2 or fPCLK/128 • Time-out detection with NMI generation and reset prewarning activation (after which a system reset will be performed) The WDT is a 16-bit timer incremented by a count rate of f PCLK/2 or fPCLK/128. This 16-bit timer is realized as two concatenated 8-bit timers. The upper 8 bits of the WDT can be preset to a user-programmable value via a watchdog service access in order to modify the watchdog expire time period. The lower 8 bits are reset on each service access. Figure 28 shows the block diagram of the WDT unit. Figure 28 WDT Block Diagram WDTREL MUX WDT Low Byte 1:2 Clear WDT Control 1:128 WDT High Byte FNMIWDT WDTIN f PCLK Logic ENWDT ENWDT_P WDTRST Overflow/Time-out Control & Window-boundary control WDTWINB . |
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