XC888LM datasheet(98/144 Pages) INFINEON

98 / 144 page

XC886/888CLM

Functional Description

Data Sheet

V0.9, 2006-12

3.16

High-Speed Synchronous Serial Interface

The High-Speed Synchronous Serial Interface (SSC) supports full-duplex and

half-duplex synchronous communication. The serial clock signal can be generated by

the SSC internally (master mode), using its own 16-bit baud-rate generator, or can be

received from an external master (slave mode). Data width, shift direction, clock polarity

and phase are programmable. This allows communication with SPI-compatible devices

or devices using other synchronous serial interfaces.

Features

•

Master and slave mode operation

– Full-duplex or half-duplex operation

•

Transmit and receive buffered

•

Flexible data format

– Programmable number of data bits: 2 to 8 bits

– Programmable shift direction: LSB or MSB shift first

– Programmable clock polarity: idle low or high state for the shift clock

– Programmable clock/data phase: data shift with leading or trailing edge of the shift

clock

•

Variable baud rate

•

Compatible with Serial Peripheral Interface (SPI)

•

Interrupt generation

– On a transmitter empty condition

– On a receiver full condition

– On an error condition (receive, phase, baud rate, transmit error)

Data is transmitted or received on lines TXD and RXD, which are normally connected to

the pins MTSR (Master Transmit/Slave Receive) and MRST (Master Receive/Slave

Transmit). The clock signal is output via line MS_CLK (Master Serial Shift Clock) or input

via line SS_CLK (Slave Serial Shift Clock). Both lines are normally connected to the pin

SCLK. Transmission and reception of data are double-buffered.

Figure 32 shows the block diagram of the SSC.

XC888LM Datasheet(PDF) 98 Page - Infineon Technologies AG