XC888LM datasheet(26/144 Pages) INFINEON

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XC886/888CLM

Functional Description

Data Sheet

V0.9, 2006-12

Functional Description

Chapter 3 provides an overview of the XC886/888 functional description.

3.1

Processor Architecture

The XC886/888 is based on a high-performance 8-bit Central Processing Unit (CPU)

that is compatible with the standard 8051 processor. While the standard 8051 processor

is designed around a 12-clock machine cycle, the XC886/888 CPU uses a 2-clock

machine cycle. This allows fast access to ROM or RAM memories without wait state.

Access to the Flash memory, however, requires an additional wait state (one machine

cycle). The instruction set consists of 45% one-byte, 41% two-byte and 14% three-byte

instructions.

The XC886/888 CPU provides a range of debugging features, including basic stop/start,

single-step execution, breakpoint support and read/write access to the data memory,

program memory and Special Function Registers (SFRs).

Figure 6 shows the CPU functional blocks.

Figure 6

CPU Block Diagram

ALU

UART

Core SFRs

16-bit Registers &

Memory Interface

Opcode Decoder

State Machine &

Power Saving

Interrupt

Controller

Multiplier / Divider

Opcode &

Immediate

Registers

Timer 0 / Timer 1

Internal Data

Memory

External SFRs

External Data

Memory

Program Memory

CCLK

Memory Wait

Reset

Legacy External Interrupts (IEN0, IEN1)

External Interrupts

Non-Maskable Interrupt

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