XC888LM datasheet(93/144 Pages) INFINEON

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XC886/888CLM

Functional Description

Data Sheet

V0.9, 2006-12

fractional divider) for generating a wide range of baud rates based on its input clock

PCLK,

see Figure 30.

Figure 30

Baud-rate Generator Circuitry

The baud rate timer is a count-down timer and is clocked by either the output of the

fractional divider (

MOD) if the fractional divider is enabled (FDCON.FDEN = 1), or the

output of the prescaler (

DIV) if the fractional divider is disabled (FDEN = 0). For baud rate

generation, the fractional divider must be configured to fractional divider mode

(FDCON.FDM = 0). This allows the baud rate control run bit BCON.R to be used to start

or stop the baud rate timer. At each timer underflow, the timer is reloaded with the 8-bit

reload value in register BG and one clock pulse is generated for the serial channel.

Enabling the fractional divider in normal divider mode (FDEN = 1 and FDM = 1) stops the

baud rate timer and nullifies the effect of bit BCON.R. See Section 3.14.

The baud rate (

BR) value is dependent on the following parameters:

•

Input clock

PCLK

•

Prescaling factor (2

BRPRE) defined by bit field BRPRE in register BCON

•

Fractional divider (STEP/256) defined by register FDSTEP

(to be considered only if fractional divider is enabled and operating in fractional

divider mode)

•

8-bit reload value (BR_VALUE) for the baud rate timer defined by register BG

FDSTEP

FDM

Adder

FDRES

FDEN&FDM

clk

Fractional Divider

Prescaler

NDOV

‘0’

FDEN

(overflow)

8-Bit Baud Rate Timer

8-Bit Reload Value

DIV

PCLK

MOD

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