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XC888LM Datasheet(PDF) 38 Page - Infineon Technologies AG |
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XC888LM Datasheet(HTML) 38 Page - Infineon Technologies AG |
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38 / 144 page  XC886/888CLM Functional Description Data Sheet 31 V0.9, 2006-12 3.2.4 XC886/888 Register Overview The SFRs of the XC886/888 are organized into groups according to their functional units. The contents (bits) of the SFRs are summarized in Chapter 3.2.4.1 to Chapter 3.2.4.14. Note: The addresses of the bitaddressable SFRs appear in bold typeface. 3.2.4.1 CPU Registers The CPU SFRs can be accessed in both the standard and mapped memory areas (RMAP = 0 or 1). Table 5 CPU Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP = 0 or 1 81H SP Reset: 07H Stack Pointer Register Bit Field SP Type rw 82H DPL Reset: 00H Data Pointer Register Low Bit Field DPL7 DPL6 DPL5 DPL4 DPL3 DPL2 DPL1 DPL0 Type rw rw rw rw rw rw rw rw 83H DPH Reset: 00H Data Pointer Register High Bit Field DPH7 DPH6 DPH5 DPH4 DPH3 DPH2 DPH1 DPH0 Type rw rw rw rw rw rw rw rw 87H PCON Reset: 00H Power Control Register Bit Field SMOD 0 GF1 GF0 0 IDLE Type rw r rw rw r rw 88H TCON Reset: 00H Timer Control Register Bit Field TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Type rwh rw rwh rw rwh rw rwh rw 89H TMOD Reset: 00H Timer Mode Register Bit Field GATE 1 T1S T1M GATE 0 T0S T0M Type rw rw rw rw rw rw 8AH TL0 Reset: 00H Timer 0 Register Low Bit Field VAL Type rwh 8BH TL1 Reset: 00H Timer 1 Register Low Bit Field VAL Type rwh 8CH TH0 Reset: 00H Timer 0 Register High Bit Field VAL Type rwh 8DH TH1 Reset: 00H Timer 1 Register High Bit Field VAL Type rwh 98H SCON Reset: 00H Serial Channel Control Register Bit Field SM0 SM1 SM2 REN TB8 RB8 TI RI Type rw rw rw rw rw rwh rwh rwh 99H SBUF Reset: 00H Serial Data Buffer Register Bit Field VAL Type rwh A2H EO Reset: 00H Extended Operation Register Bit Field 0 TRAP_ EN 0 DPSE L0 Type r rw r rw |
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