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XC888LM Datasheet(PDF) 39 Page - Infineon Technologies AG |
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XC888LM Datasheet(HTML) 39 Page - Infineon Technologies AG |
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39 / 144 page  XC886/888CLM Functional Description Data Sheet 32 V0.9, 2006-12 3.2.4.2 MDU Registers The MDU SFRs can be accessed in the mapped memory area (RMAP = 1). A8H IEN0 Reset: 00H Interrupt Enable Register 0 Bit Field EA 0 ET2 ES ET1 EX1 ET0 EX0 Type rw r rwrw rw rw rwrw B8H IP Reset: 00H Interrupt Priority Register Bit Field 0 PT2 PS PT1 PX1 PT0 PX0 Type r rwrw rw rw rwrw B9H IPH Reset: 00H Interrupt Priority High Register Bit Field 0 PT2H PSH PT1H PX1H PT0H PX0H Type r rwrw rw rw rwrw D0H PSW Reset: 00H Program Status Word Register Bit Field CY AC F0 RS1 RS0 OV F1 P Type rwh rwh rw rw rw rwh rw rh E0H ACC Reset: 00H Accumulator Register Bit Field ACC7 ACC6 ACC5 ACC4 ACC3 ACC2 ACC1 ACC0 Type rw rw rw rw rw rw rw rw E8H IEN1 Reset: 00H Interrupt Enable Register 1 Bit Field ECCIP 3 ECCIP 2 ECCIP 1 ECCIP 0 EXM EX2 ESSC EADC Type rw rw rw rw rw rw rw rw F0H B Reset: 00H B Register Bit Field B7 B6 B5 B4 B3 B2 B1 B0 Type rw rw rw rw rw rw rw rw F8H IP1 Reset: 00H Interrupt Priority 1 Register Bit Field PCCIP 3 PCCIP 2 PCCIP 1 PCCIP 0 PXM PX2 PSSC PADC Type rw rw rw rw rw rw rw rw F9H IPH1 Reset: 00H Interrupt Priority 1 High Register Bit Field PCCIP 3H PCCIP 2H PCCIP 1H PCCIP 0H PXMH PX2H PSSC H PADC H Type rw rw rw rw rw rw rw rw Table 6 MDU Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP = 1 B0H MDUSTAT Reset: 00H MDU Status Register Bit Field 0 BSY IERR IRDY Type r rh rwh rwh B1H MDUCON Reset: 00H MDU Control Register Bit Field IE IR RSEL STAR T OPCODE Type rw rw rw rwh rw B2H MD0 Reset: 00H MDU Operand Register 0 Bit Field DATA Type rw B2H MR0 Reset: 00H MDU Result Register 0 Bit Field DATA Type rh B3H MD1 Reset: 00H MDU Operand Register 1 Bit Field DATA Type rw Table 5 CPU Register Overview (cont’d) Addr Register Name Bit 7 6 5 4 3 2 1 0 |
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