XC888LM datasheet(84/144 Pages) INFINEON

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XC886/888CLM

Functional Description

Data Sheet

V0.9, 2006-12

3.8.2

Clock Management

The CGU generates all clock signals required within the microcontroller from a single

clock,

sys. During normal system operation, the typical frequencies of the different

modules are as follow:

•

CPU clock: CCLK, SCLK = 24 MHz

•

Fast clock (used by MultiCAN): FCLK = 24 or 48 MHz

•

Peripheral clock: PCLK = 24 MHz

•

Flash Interface clock: CCLK2 = 48 MHz and CCLK = 24 MHz

In addition, different clock frequencies can be output to pin CLKOUT (P0.0 or P0.7). The

clock output frequency, which is derived from the clock output divider (bit COREL), can

further be divided by 2 using toggle latch (bit TLEN is set to 1). The resulting output

frequency has a 50% duty cycle. Figure 26 shows the clock distribution of the

XC886/888.

Figure 26

Clock Generation from

sys

PLL

N,P,K

fsys=

96MHz

CLKREL

CCLK

SCLK

PCLK

CCLK2

CORE

Peripherals

FLASH

Interface

OSC

CLKOUT

fosc

COREL

COUTS

Toggle

Latch

TLEN

MultiCAN

FCLK

FCCFG

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