HD6417618 datasheet(276/646 Pages) RENESAS

276 / 646 page

Section 11 Ethernet Controller (EtherC)

Rev. 6.00 Jun. 12, 2007 Page 244 of 610

REJ09B0131-0600

11.3.16

Too-Long Frame Receive Counter Register (TLFRCR)

TLFRCR is a 32-bit counter that indicates the number of frames received with a length exceeding

the value specified by the receive frame length register (RFLR). When the value in this register

reaches H'FFFFFFFF, the count is halted. TLFRCR is not incremented when a frame containing

residual bits is received. In this case, the reception of the frame is indicated in the residual-bit

frame counter register (RFCR). The counter value is cleared to 0 by a write to this register with

any value.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 0 TLFC31 to

TLFC0

All 0

R/W

Too-Long Frame Receive Count

These bits indicate the count of frames received with

a length exceeding the value in RFLR.

11.3.17

Residual-Bit Frame Counter Register (RFCR)

RFCR is a 32-bit counter that indicates the number of frames received containing residual bits

(less than an 8-bit unit). When the value in this register reaches H'FFFFFFFF, the count is halted.

The counter value is cleared to 0 by a write to this register with any value.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 0 RFC31 to

RFC0

All 0

R/W

Residual-Bit Frame Count

These bits indicate the count of frames received

containing residual bits.

11.3.18

Multicast Address Frame Counter Register (MAFCR)

MAFCR is a 32-bit counter that indicates the number of frames received with a specified multicast

address. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter

value is cleared to 0 by a write to this register with any value.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 0 MAFC31 to

MAFC0

All 0

R/W

Multicast Address Frame Count

These bits indicate the count of multicast frames

received.

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