HD6417618 datasheet(88/646 Pages) RENESAS

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Section 3 Cache

Rev. 6.00 Jun. 12, 2007 Page 56 of 610

REJ09B0131-0600

3.3.2

Read Access

Read Hit: In a read access, instructions and data are transferred from the cache to the CPU. The

LRU bits are updated so that they point to the most recently hit way.

Read Miss: An external bus cycle starts and the entry is updated. The way to be replaced is shown

in table 3.1. Data is updated in units of 16 bytes by updating the entry. When the desired

instruction or data is loaded from external memory to the cache, the instruction or data is

transferred to the CPU in parallel. When it is loaded to the cache, the U bit is cleared to 0, the V

bit is set to 1, the LRU bits are updated so that they point to the most recently hit way. When the U

bit of the entry which is to be replaced by entry updating in write-back mode is 1, the cache-

update cycle starts after the entry is transferred to the write-back buffer. After the cache completes

its update cycle, the write-back buffer writes the entry back to the memory. Transfer is in 16-byte

units.

3.3.3

Write Access

Write Hit: In a write access in write-back mode, the data is written to the cache and no external

memory write cycle is generated. The U bit of the entry that has been written to is set to 1, and the

LRU bits are updated to indicate that the hit way is the most recently hit way. In write-through

mode, the data is written to the cache and an external memory write cycle is generated. The U bit

of the entry that has been written to is not updated, and the LRU bits are updated to indicate that

the hit way is the most recently hit way.

Write Miss: In write-back mode, an external write cycle starts when a write miss occurs, and the

entry is updated. The way to be replaced is shown in table 3.1. When the U bit of the entry which

is to be replaced by entry updating is 1, the cache-update cycle starts after the entry has been

transferred to the write-back buffer. Data is written to the cache and the U bit and the V bit are set

to 1. The LRU bits are updated to indicate that the replaced way is the most recently updated way.

After the cache has completed its update cycle, the write-back buffer writes the entry back to the

memory. Transfer is in 16-byte units. In write-through mode, no write to cache occurs in a write

miss; the write is only to the external memory.

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