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HD6417618 Datasheet(PDF) 74 Page - Renesas Technology Corp

Part # HD6417618
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
PDF  646 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6417618 Datasheet(HTML) 74 Page - Renesas Technology Corp

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Section 2 CPU
Rev. 6.00 Jun. 12, 2007 Page 42 of 610
REJ09B0131-0600
Instruction
Operation
Code
Execution
Cycles
T Bit
DMULU.L
Rm,Rn
Unsigned operation of
Rn
× Rm → MACH,
MACL 32
× 32 → 64 bits
0011nnnnmmmm0101
2 to 5*
DT
Rn
Rn - 1
→ Rn, if Rn = 0, 1 →
T, else 0
→ T
0100nnnn00010000
1
Comparison
result
EXTS.B Rm,Rn
A byte in Rm is sign-
extended
→ Rn
0110nnnnmmmm1110
1
EXTS.W Rm,Rn
A word in Rm is sign-
extended
→ Rn
0110nnnnmmmm1111
1
EXTU.B Rm,Rn
A byte in Rm is zero-
extended
→ Rn
0110nnnnmmmm1100
1
EXTU.W Rm,Rn
A word in Rm is zero-
extended
→ Rn
0110nnnnmmmm1101
1
MAC.L
@Rm+,@Rn+
Signed operation of (Rn)
× (Rm) + MAC → MAC,
32
× 32 + 64 → 64 bits
0000nnnnmmmm1111
2 to 5*
MAC.W
@Rm+,@Rn+
Signed operation of (Rn)
× (Rm) + MAC → MAC,
16
× 16 + 64 → 64 bits
0100nnnnmmmm1111
2 to 4*
MUL.L
Rm,Rn
Rn
× Rm → MACL
32
× 32 → 32 bits
0000nnnnmmmm0111
2 to 5*
MULS.W Rm,Rn
Signed operation of Rn
× Rm → MAC
16
× 16 → 32 bits
0010nnnnmmmm1111
1 (3)*
MULU.W Rm,Rn
Unsigned operation of
Rn
× Rm → MAC
16
× 16 → 32 bits
0010nnnnmmmm1110
1 (3)*
NEG
Rm,Rn
0-Rm
→ Rn
0110nnnnmmmm1011
1
NEGC
Rm,Rn
0-Rm-T
→ Rn,
Borrow
→ T
0110nnnnmmmm1010
1
Borrow
SUB
Rm,Rn
Rn-Rm
→ Rn
0011nnnnmmmm1000
1



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