HD6417618 datasheet(41/646 Pages) RENESAS

41 / 646 page

Section 1 Overview

Rev. 6.00 Jun. 12, 2007 Page 9 of 610

REJ09B0131-0600

Classifi-

cation

Abbr.

I/O

Pin Name

Description

System

control

RES

Input

Power-On

Reset

This LSI enters the reset state when this signal goes low.

Interrupt

NMI

Input

Non-Maskable

Interrupt

Non-maskable interrupt request signal. When this pin is not

in use, this signal must be fixed high.

IRQ7 to

IRQ0

Input

Interrupt

Request 7 to 0

Maskable interrupt request pins.

Level-input or edge-input detection can be selected. When

the edge-input detection is selected, the rising or falling edge

can also be selected.

Address

bus

A25 to A0

Output Address Bus

Outputs addresses.

Data bus

D15 to D0

Input/

output

Data Bus

16-bit bidirectional bus

Bus

control

CS0, CS3,

CS4, CS5B,

CS6B

Output Chip Select 0,

3, 4, 5B, 6B

Chip select signals for external memory and devices.

Output Read

Indicates that data is read from an external device.

RD/

Output Read/Write

Read/write signal

Output Bus Cycle

Start

Indicates start of a bus cycle.

WE1

Output Upper Side

Write

Indicates that bits 15 to 8 of data of external memory or

devices are written to.

WE0

Output Lower Side

Write

Indicates that bits 7 to 0 of data of external memory or

devices are written to.

WAIT

Input

Wait

Input pin used to insert wait cycles when accessing the

external space

RAS

Output RAS

Connects to the

RAS pin of SDRAM.

CAS

Output CAS

Connects to the

CAS pin of SDRAM.

CKE

Output Clock Enable

Connects to the CKE pin of SDRAM.

DQMLU

Output Upper Side

Select

Selects bits 15 to 8 of SDRAM data bus.

DQMLL

Output Lower Side

Select

Selects bits 7 to 0 of SDRAM data bus.

CE1A

Output PCMCIA Card

Select Lower

Side

Chip enable for PCMCIA allocated to area 5

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