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HD6417618 Datasheet(PDF) 75 Page - Renesas Technology Corp

Part # HD6417618
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
PDF  646 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6417618 Datasheet(HTML) 75 Page - Renesas Technology Corp

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Section 2 CPU
Rev. 6.00 Jun. 12, 2007 Page 43 of 610
REJ09B0131-0600
Instruction
Operation
Code
Execution
Cycles
T Bit
SUBC Rm,Rn
Rn-Rm–T
→ Rn,
Borrow
→ T
0011nnnnmmmm1010
1
Borrow
SUBV Rm,Rn
Rn-Rm
→ Rn,
Underflow
→ T
0011nnnnmmmm1011
1
Overflow
Note:
*
Indicates the number of execution cycles for normal operation. The values in
parentheses indicate the number of execution cycles when conflicts occur with the
previous or next instruction.
• Logic Operation Instructions
Instruction
Operation
Code
Execution
Cycles
T Bit
AND
Rm,Rn
Rn & Rm
→ Rn
0010nnnnmmmm1001
1
AND
#imm,R0
R0 & imm
→ R0
11001001iiiiiiii
1
AND.B #imm,@(R0,GBR)
(R0 + GBR) & imm
→
(R0 + GBR)
11001101iiiiiiii
3
NOT
Rm,Rn
~Rm
→ Rn
0110nnnnmmmm0111
1
OR
Rm,Rn
Rn | Rm
→ Rn
0010nnnnmmmm1011
1
OR
#imm,R0
R0 | imm
→ R0
11001011iiiiiiii
1
OR.B
#imm,@(R0,GBR)
(R0 + GBR) | imm
→
(R0 + GBR)
11001111iiiiiiii
3
TAS.B @Rn
If (Rn) is 0, 1
→ T;
1
→ MSB of (Rn)
0100nnnn00011011
4
Test result
TST
Rm,Rn
Rn & Rm; if the result
is 0, 1
→ T
0010nnnnmmmm1000
1
Test result
TST
#imm,R0
R0 & imm; if the result
is 0, 1
→ T
11001000iiiiiiii
1
Test result
TST.B #imm,@(R0,GBR)
(R0 + GBR) & imm;
if the result is 0, 1
→ T
11001100iiiiiiii
3
Test result
XOR
Rm,Rn
Rn ^ Rm
→ Rn
0010nnnnmmmm1010
1
XOR
#imm,R0
R0 ^ imm
→ R0
11001010iiiiiiii
1
XOR.B #imm,@(R0,GBR)
(R0 + GBR) ^ imm
→
(R0 + GBR)
11001110iiiiiiii
3



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