HD6417618 datasheet(30/646 Pages) RENESAS

30 / 646 page

Rev. 6.00 Jun. 12, 2007 Page xxx of xxxii

Table 7.2

Address Map 1 (CMNCR.MAP = 0) .................................................................... 110

Table 7.3

Address Map 2 (CMNCR.MAP = 1) .................................................................... 111

Table 7.4

Correspondence between External Pin (MD3), Memory Type,

and Bus Width for CS0......................................................................................... 112

Table 7.5

Correspondence between External Pin (MD5) and Endians................................. 112

Table 7.6

16-Bit External Device/Big Endian Access and Data Alignment......................... 142

Table 7.7

8-Bit External Device/Big Endian Access and Data Alignment........................... 143

Table 7.8

16-Bit External Device/Little Endian Access and Data Alignment ...................... 144

Table 7.9

8-Bit External Device/Little Endian Access and Data Alignment ........................ 145

Table 7.10

Relationship between Register Settings and Address Multiplex Output (1)......... 155

Table 7.11

Relationship between Register Settings and Address Multiplex Output (2)......... 156

Table 7.12

Relationship between Register Settings and Address Multiplex Output (3)......... 157

Table 7.13

Relationship between Register Settings and Address Multiplex Output (4)......... 158

Table 7.14

Relationship between Register Settings and Address Multiplex Output (5)......... 159

Table 7.15

Relationship between Register Settings and Address Multiplex Output (6)......... 160

Table 7.16

Relationship between Access Size and Number of Bursts.................................... 161

Table 7.17

Access Address for SDRAM Mode Register Write.............................................. 178

Section 8 Clock Pulse Generator (CPG)

Table 8.1

Pin Configuration.................................................................................................. 196

Table 8.2

Mode Control Pins and Clock Operating Modes .................................................. 196

Table 8.3

Possible Combination of Clock Modes and FRQCR Values................................ 197

Section 10 Power-Down Modes

Table 10.1

States of Power-Down Modes .............................................................................. 216

Table 10.2

Pin Configuration.................................................................................................. 217

Table 10.3

Section 11 Ethernet Controller (EtherC)

Table 11.1

Pin Configuration.................................................................................................. 229

Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Table 12.1

EESR Bits for which This Problem can Occur and Reflection of

Interrupt Sources in the Descriptor ....................................................................... 298

Table 12.2

Reference Values for Maximum Specified Time.................................................. 314

Section 14 Serial Communication Interface with FIFO (SCIF)

Table 14.1

SCIF Pins.............................................................................................................. 328

Table 14.2

SCSMR Settings ................................................................................................... 347

Table 14.3

Bit Rates and SCBRR Settings in Asynchronous Mode....................................... 347

Table 14.4

Bit Rates and SCBRR Settings in Synchronous Mode ......................................... 350

Table 14.5

Maximum Bit Rates for Various Frequencies with Baud Rate Generator

(Asynchronous Mode) .......................................................................................... 351

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