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HD6417618 Datasheet(PDF) 64 Page - Renesas Technology Corp |
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HD6417618 Datasheet(HTML) 64 Page - Renesas Technology Corp |
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64 / 646 page  Section 2 CPU Rev. 6.00 Jun. 12, 2007 Page 32 of 610 REJ09B0131-0600 Table 2.9 Instruction Formats Instruction Format Source Operand Destination Operand Sample Instruction 0 type xxxx xxxx xxxx xxxx 15 0 NOP nnnn : register direct MOVT Rn Control register or system register nnnn : register direct STS MACH,Rn n type xxxx nnnn xxxx xxxx 15 0 Control register or system register nnnn : pre- decrement register indirect STC.L SR,@-Rn mmmm : register direct Control register or system register LDC Rm,SR mmmm : post- increment register indirect Control register or system register LDC.L @Rm+,SR mmmm : register indirect JMP @Rm m type xxxx mmmm xxxx xxxx 15 0 PC relative using Rm BRAF Rm |
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