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HD6417618 Datasheet(PDF) 68 Page - Renesas Technology Corp |
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HD6417618 Datasheet(HTML) 68 Page - Renesas Technology Corp |
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68 / 646 page  Section 2 CPU Rev. 6.00 Jun. 12, 2007 Page 36 of 610 REJ09B0131-0600 Type Kinds of Instruction Op Code Function Number of Instructions MULS Signed multiplication MULU Unsigned multiplication NEG Sign inversion NEGC Sign inversion with borrow SUB Binary subtraction SUBC Binary subtraction with carry Arithmetic operation instructions 21 SUBV Binary subtraction with underflow 33 AND Logical AND NOT Bit inversion OR Logical OR TAS Memory test and bit setting TST T bit setting for logical AND Logic operation instructions 6 XOR Exclusive logical OR 14 ROTL 1-bit left shift ROTR 1-bit right shift ROTCL 1-bit left shift with T bit ROTCR 1-bit right shift with T bit SHAL Arithmetic 1-bit left shift SHAR Arithmetic 1-bit right shift SHLL Logical 1-bit left shift SHLLn Logical n-bit left shift SHLR Logical 1-bit right shift Shift instructions 10 SHLRn Logical n-bit right shift 14 |
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