HD6417618 datasheet(14/646 Pages) RENESAS

14 / 646 page

Rev. 6.00 Jun. 12, 2007 Page xiv of xxxii

10.3.2 Standby Control Register 2 (STBCR2)................................................................. 219

10.3.3 Standby Control Register 3 (STBCR3)................................................................. 220

10.3.4 Standby Control Register 4 (STBCR4)................................................................. 221

10.4

Sleep Mode ........................................................................................................................ 222

10.4.1 Transition to Sleep Mode...................................................................................... 222

10.4.2 Canceling Sleep Mode .......................................................................................... 222

10.5

Software Standby Mode..................................................................................................... 223

10.5.1 Transition to Software Standby Mode .................................................................. 223

10.5.2 Canceling Software Standby Mode ...................................................................... 224

10.6

Module Standby Mode....................................................................................................... 225

10.6.1 Transition to Module Standby Mode .................................................................... 225

10.6.2 Canceling Module Standby Function.................................................................... 225

Section 11 Ethernet Controller (EtherC) ............................................................. 227

11.1

Features.............................................................................................................................. 227

11.2

Input/Output Pins...............................................................................................................229

11.3

Register Description .......................................................................................................... 231

11.3.1 EtherC Mode Register (ECMR)............................................................................ 232

11.3.2 EtherC Status Register (ECSR) ............................................................................ 235

11.3.3 EtherC Interrupt Permission Register (ECSIPR) .................................................. 237

11.3.4 PHY Interface Register (PIR) ............................................................................... 238

11.3.5 MAC Address High Register (MAHR) ................................................................ 239

11.3.6 MAC Address Low Register (MALR) ................................................................. 239

11.3.7 Receive Frame Length Register (RFLR) .............................................................. 240

11.3.8 PHY Status Register (PSR)................................................................................... 241

11.3.9 Transmit Retry Over Counter Register (TROCR) ................................................ 241

11.3.10 Delayed Collision Detect Counter Register (CDCR)............................................ 242

11.3.11 Lost Carrier Counter Register (LCCR)................................................................. 242

11.3.12 Carrier Not Detect Counter Register (CNDCR) ................................................... 242

11.3.13 CRC Error Frame Counter Register (CEFCR) ..................................................... 243

11.3.14 Frame Receive Error Counter Register (FRECR)................................................. 243

11.3.15 Too-Short Frame Receive Counter Register (TSFRCR) ...................................... 243

11.3.16 Too-Long Frame Receive Counter Register (TLFRCR) ...................................... 244

11.3.17 Residual-Bit Frame Counter Register (RFCR) ..................................................... 244

11.3.18 Multicast Address Frame Counter Register (MAFCR) ........................................ 244

11.3.19 IPG Register (IPGR)............................................................................................. 245

11.3.20 Automatic PAUSE Frame Set Register (APR) ..................................................... 245

11.3.21 Manual PAUSE Frame Set Register (MPR) ......................................................... 246

11.3.22 Automatic PAUSE Frame Retransfer Count Set Register (TPAUSER) ............... 246

11.4

Operation ........................................................................................................................... 247

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