HD6417618 datasheet(12/646 Pages) RENESAS

12 / 646 page

Rev. 6.00 Jun. 12, 2007 Page xii of xxxii

Section 6 Interrupt Controller (INTC)................................................................... 81

6.1

Features................................................................................................................................ 81

6.2

Input/Output Pins................................................................................................................. 83

6.3

Register Descriptions ...........................................................................................................83

6.3.1

Interrupt Control Register 0 (ICR0)........................................................................ 84

6.3.2

IRQ Control Register (IRQCR) .............................................................................. 85

6.3.3

IRQ Status register (IRQSR) .................................................................................. 88

6.3.4

Interrupt Priority Registers A to E (IPRA to IPRE)................................................ 93

6.4

Interrupt Sources.................................................................................................................. 95

6.4.1

External Interrupts .................................................................................................. 95

6.4.2

On-Chip Peripheral Module Interrupts ................................................................... 97

6.4.3

User Break Interrupt ............................................................................................... 97

6.4.4

H-UDI Interrupt ...................................................................................................... 97

6.5

Interrupt Exception Handling Vector Table......................................................................... 98

6.6

Interrupt Operation ............................................................................................................ 100

6.6.1

Interrupt Sequence ................................................................................................ 100

6.6.2

Stack after Interrupt Exception Handling ............................................................. 102

6.7

Interrupt Response Time.................................................................................................... 102

Section 7 Bus State Controller (BSC) ................................................................. 105

7.1

Features.............................................................................................................................. 105

7.2

Input/Output Pins...............................................................................................................108

7.3

Area Overview...................................................................................................................109

7.3.1

Area Division........................................................................................................ 109

7.3.2

Shadow Area......................................................................................................... 109

7.3.3

Address Map......................................................................................................... 110

7.3.4

Area 0 Memory Type and Memory Bus Width .................................................... 112

7.3.5

Data Alignment..................................................................................................... 112

7.4

Register Descriptions ......................................................................................................... 113

7.4.1

Common Control Register (CMNCR) .................................................................. 114

7.4.2

CSn Space Bus Control Register (CSnBCR) (n = 0, 2, 3, 4, 5B, 6B) ................... 115

7.4.3

CSn Space Wait Control Register (CSnWCR) (n = 0, 3, 4, 5B, 6B) .................... 120

7.4.4

SDRAM Control Register (SDCR)....................................................................... 136

7.4.5

Refresh Timer Control/Status Register (RTCSR)................................................. 137

7.4.6

Refresh Timer Counter (RTCNT)......................................................................... 139

7.4.7

Refresh Time Constant Register (RTCOR) .......................................................... 140

7.5

Operation ........................................................................................................................... 141

7.5.1

Endian/Access Size and Data Alignment.............................................................. 141

7.5.2

Normal Space Interface ........................................................................................ 146

7.5.3

Access Wait Control ............................................................................................. 150

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