HD6417618 datasheet(84/646 Pages) RENESAS

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Section 3 Cache

Rev. 6.00 Jun. 12, 2007 Page 52 of 610

REJ09B0131-0600

3.2

The cache has the following registers. For details on register addresses and register states during

each process, refer to section 20, List of Registers.

• Cache control register 1 (CCR1)

• Cache control register 3 (CCR3)*

Note: * Supported only by the SH7618.

3.2.1

Cache Control Register 1 (CCR1)

The cache is enabled or disabled by the CE bit in CCR1. CCR1 also has the CF bit (which

invalidates all cache entries), and the WT and CB bits (which select either write-through mode or

write-back mode). Programs that change the contents of CCR1 should be placed in the address

space that is not cached.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 4

—

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

R/W

Cache Flush

Writing 1 flushes all cache entries meaning that it

clears the V, U, and LRU bits of all cache entries to

0. This bit is always read as 0. Write-back to

external memory is not performed when the cache is

flushed.

R/W

Write-Back

Indicates the cache operating mode for H'80000000

to H'9FFFFFFF.

0: Write-through mode

1: Write-back mode

R/W

Write-Through

Indicates the cache operating mode for H'00000000

to H'7FFFFFFF and H'C0000000 to H'DFFFFFFF.

0: Write-back mode

1: Write-through mode

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