HD6417618 datasheet(34/646 Pages) RENESAS

34 / 646 page

Section 1 Overview

Rev. 6.00 Jun. 12, 2007 Page 2 of 610

REJ09B0131-0600

1.1

Features

The features of this LSI are shown below.

CPU:

• Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer)

architecture

• Instruction length: 16-bit fixed length for improved code efficiency

• Load-store architecture (basic operations are executed between registers)

• Sixteen 32-bit general registers

• Five-stage pipeline

• On-chip multiplier: Multiplication operations (32 bits × 32 bits → 64 bits) executed in two to

five cycles

• C language-oriented 62 basic instructions

Note:

Some specifications on the slot illegal instruction differ from the conventional SH2 core.

For details, see section 5.8, Usage Notes, in section 5, Exception Handling.

User break controller (UBC):

• Address, data value, access type, and data size are available for setting as break conditions

• Supports the sequential break function

• Two break channels

U memory:

• 4 kbytes

Cache memory:

• Unified cache, mixture of instructions and data

• 4-way set associative type

• Selection of write-back or write-through mode

• 4 kbytes (SH7618), 16kbytes (SH7618A)

HD6417618 Datasheet(PDF) 34 Page - Renesas Technology Corp