HD6417618 datasheet(70/646 Pages) RENESAS

70 / 646 page

Section 2 CPU

Rev. 6.00 Jun. 12, 2007 Page 38 of 610

REJ09B0131-0600

The instruction code, operation, and execution cycles of the instructions are listed in the following

tables, classified by type.

Instruction

Instruction Code

Summary of

Operation

Execution

Cycles

T Bit

Indicated by mnemonic.

Explanation of Symbols

OP.Sz SRC, DEST

OP:

Operation code

Sz:

Size

SRC: Source

DEST: Destination

Rm: Source register

Rn:

Destination

imm: Immediate data

disp: Displacement*

Indicated in MSB

↔

LSB order.

Explanation of Symbols

mmmm: Source register

nnnn: Destination

0000: R0

0001: R1

.........

1111: R15

iiii:

Immediate data

dddd: Displacement

Indicates summary of

operation.

Explanation of Symbols

→, ←: Transfer direction

(xx):

Memory operand

M/Q/T: Flag bits in SR

Logical AND of each bit

Logical OR of each bit

Exclusive logical OR of

each bit

–:

Logical NOT of each bit

<<n: n-bit left shift

>>n: n-bit right shift

Value when no

wait cycles are

inserted*

Value of T bit after

instruction is

executed

Explanation of

Symbols

: No change

Notes: 1. The table shows the minimum number of execution states. In practice, the number of

instruction execution states will be increased in cases such as the following:

•

When there is contention between an instruction fetch and a data access

•

When the destination register of a load instruction (memory

→ register) is also used

by the following instruction

Scaled (

×1, ×2, or ×4) according to the instruction operand size, etc.

For details, see SH-1/SH-2/SH-DSP Software Manual.

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