HD6417618 datasheet(89/646 Pages) RENESAS

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Section 3 Cache

Rev. 6.00 Jun. 12, 2007 Page 57 of 610

REJ09B0131-0600

3.3.4

Write-Back Buffer

When the U bit of the entry to be replaced in write-back mode is 1, the entry must be written back

to the external memory. To increase performance, the entry to be replaced is first transferred to the

write-back buffer and fetching of new entries to the cache takes priority over writing back to the

external memory. After the fetching of new entries to the cache completes, the write-back buffer

writes the entry back to the external memory. During the write-back cycles, the cache can be

accessed. The write-back buffer can hold one line of cache data (16 bytes) and its physical

address. Figure 3.3 shows the configuration of the write-back buffer.

Longword 0 Longword 1 Longword 2 Longword 3

PA (31 to 4)

PA (31 to 4):

Longword 0 to 3:

Physical address to be written to external memory

One line of cache data to be written to external memory

Figure 3.3 Write-Back Buffer Configuration

3.3.5

Coherency of Cache and External Memory

Coherency between the cache and the external memory must be ensured by software. When

memory shared by this LSI and another device is allocated to a cacheable address space, invalidate

and write back the cache by accessing the memory-mapped cache, as required. Memory that is

shared by the CPU and E-DMAC of this LSI should also be handled in this way.

HD6417618 Datasheet(PDF) 89 Page - Renesas Technology Corp