HD6417618 datasheet(13/646 Pages) RENESAS

13 / 646 page

Rev. 6.00 Jun. 12, 2007 Page xiii of xxxii

7.5.4

Extension of Chip Select (

CSn) Assertion Period................................................. 152

7.5.5

SDRAM Interface ................................................................................................. 153

7.5.6

Byte-Selection SRAM Interface ........................................................................... 179

7.5.7

PCMCIA Interface ................................................................................................ 183

7.5.8

Wait between Access Cycles ................................................................................ 190

7.5.9

Others.................................................................................................................... 190

Section 8 Clock Pulse Generator (CPG)..............................................................193

8.1

Features.............................................................................................................................. 193

8.2

Input/Output Pins ...............................................................................................................196

8.3

Clock Operating Modes ..................................................................................................... 196

8.4

Register Descriptions ......................................................................................................... 198

8.4.1

Frequency Control Register (FRQCR) ................................................................. 198

8.4.2

PHY-LSI Clock Frequency Control Register (MCLKCR) ................................... 200

8.4.3

Usage Notes .......................................................................................................... 201

8.5

Changing Frequency .......................................................................................................... 202

8.5.1

Changing Multiplication Ratio ............................................................................. 202

8.5.2

Changing Division Ratio....................................................................................... 203

8.5.3

Changing Clock Operating Mode ......................................................................... 203

8.6

Notes on Board Design ...................................................................................................... 205

Section 9 Watchdog Timer (WDT) .....................................................................207

9.1

Features.............................................................................................................................. 207

9.2

Register Descriptions ......................................................................................................... 209

9.2.1

Watchdog Timer Counter (WTCNT).................................................................... 209

9.2.2

Watchdog Timer Control/Status Register (WTCSR)............................................ 209

9.2.3

Notes on Register Access...................................................................................... 211

9.3

WDT Operation ................................................................................................................. 212

9.3.1

Canceling Software Standbys ............................................................................... 212

9.3.2

Changing Frequency ............................................................................................. 213

9.3.3

Using Watchdog Timer Mode .............................................................................. 213

9.3.4

Using Interval Timer Mode .................................................................................. 214

9.4

Usage Note......................................................................................................................... 214

Section 10 Power-Down Modes ..........................................................................215

10.1

Features.............................................................................................................................. 215

10.1.1 Types of Power-Down Modes .............................................................................. 215

10.2

Input/Output Pins ...............................................................................................................217

10.3

Register Descriptions ......................................................................................................... 217

10.3.1 Standby Control Register (STBCR)...................................................................... 218

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