HD6417618 datasheet(43/646 Pages) RENESAS

43 / 646 page

Section 1 Overview

Rev. 6.00 Jun. 12, 2007 Page 11 of 610

REJ09B0131-0600

Classifi-

cation

Abbr.

I/O

Pin Name

Description

Ethernet

controller

MDC

Output Management

Clock

Timing reference input for transfer information on the MDIO

MDIO

Input/

output

Management

Data I/O

Bidirectional pin for management information transfer

WOL

Output MAGIC Packet

Receive

Indicates that a Magic Packet

TM* has received.

LNKSTA

Input

Link Status

Input pin for a link state from a PHY LSI.

EXOUT

Output General output Output pin to external devices

TXD2 to

TXD0

Output Transmit Data Transmit data pins

RXD2 to

RXD0

Input

Receive Data

Receive data pins

Serial

communic

ations

interface

with FIFO

SCK2 to

SCK0

Input/

output

Serial clock

Clock input pins

RTS1 and

RTS0

Output Transmit

Request

Modem control pin. Supported only by SCIF0 and SCIF1.

CTS1 and

CTS0

Input

Transmit

Enable

Modem control pin. Supported only by SCIF0 and SCIF1.

Host

interface

HIFD15 to

HIFD0

Input/

output

HIF Data Bus

Address, data, and command input/output pins for the HIF.

HIFCS

Input

HIF Chip

Select

Chip select input for the HIF

HIFRS

Input

HIF Register

Select

Controls the access type switching for the HIF.

HIFWR

Input

HIF Write

Write strobe signal

HIFRD

Input

HIF Read

Read strobe signal

HIFINT

Output HIF Interrupt

Interrupt request to external devices by the HIF

HIFMD

Input

HIF Mode

Specifies HIF boot mode.

HIFDREQ

Output HIF DMAC

Transfer

Request

Requests DMAC transfer for the HIFRAM to external

devices.

HIFRDY

Output HIF Boot

Ready

Indicates that a reset of the HIF has been cleared in this LSI

and the HIF is ready for accesses to it.

HIFEBL

Input

HIF Pin

Enable

HIF pins other than this pin are enabled by driving this pin

high.

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