HD6417618 datasheet(24/646 Pages) RENESAS

24 / 646 page

Rev. 6.00 Jun. 12, 2007 Page xxiv of xxxii

Section 14 Serial Communication Interface with FIFO (SCIF)

Figure 14.1 Block Diagram of SCIF........................................................................................... 327

Figure 14.2 Example of Data Format in Asynchronous Communication

(8-Bit Data with Parity and Two Stop Bits)............................................................ 364

Figure 14.3 Sample Flowchart for SCIF Initialization ............................................................... 367

Figure 14.4 Sample Flowchart for Transmitting Serial Data...................................................... 368

Figure 14.5 Example of Transmit Operation (8-Bit Data, Parity, One Stop Bit)........................ 370

Figure 14.6 Example of Operation Using Modem Control (

CTS).............................................. 370

Figure 14.7 Sample Flowchart for Receiving Serial Data .......................................................... 371

Figure 14.8 Sample Flowchart for Receiving Serial Data (cont)................................................ 372

Figure 14.9 Example of SCIF Receive Operation (8-Bit Data, Parity, One Stop Bit)................ 374

Figure 14.10 Example of Operation Using Modem Control (

RTS)............................................ 374

Figure 14.11 Data Format in Synchronous Communication ...................................................... 375

Figure 14.12 Sample Flowchart for SCIF Initialization ............................................................. 377

Figure 14.13 Sample Flowchart for Transmitting Serial Data.................................................... 378

Figure 14.14 Example of SCIF Transmit Operation................................................................... 379

Figure 14.15 Sample Flowchart for Receiving Serial Data (1)................................................... 380

Figure 14.16 Sample Flowchart for Receiving Serial Data (2)................................................... 380

Figure 14.17 Example of SCIF Receive Operation .................................................................... 381

Figure 14.18 Sample Flowchart for Transmitting/Receiving Serial Data................................... 382

Figure 14.19 RTSIO Bit, RTSDT bit, and

RTS Pin ................................................................... 384

Figure 14.20 CTSIO Bit, CTSDT bit, and

CTS Pin ................................................................... 385

Figure 14.21 SCKIO Bit, SCKDT bit, and SCK Pin .................................................................. 386

Figure 14.22 SPBIO Bit, SPBDT bit, and TxD Pin.................................................................... 386

Figure 14.23 SPBDT bit and RxD Pin........................................................................................ 387

Figure 14.24 Receive Data Sampling Timing in Asynchronous Mode ...................................... 389

Section 15 Host Interface (HIF)

Figure 15.1 Block Diagram of HIF............................................................................................. 392

Figure 15.2 HIF Connection Example........................................................................................ 394

Figure 15.3 Basic Timing for HIF Interface ............................................................................... 410

Figure 15.4 HIFIDX Write and HIFGSR Read .......................................................................... 411

Figure 15.5 HIF Register Settings .............................................................................................. 411

Figure 15.6 Consecutive Data Writing to HIFRAM................................................................... 412

Figure 15.7 Consecutive Data Reading from HIFRAM ............................................................. 413

Figure 15.8 HIFDREQ Timing (When DMD = 0 and DPOL = 0)............................................. 413

Figure 15.9 HIFDREQ Timing (When DMD = 0 and DPOL = 1)............................................. 414

Figure 15.10 HIFDREQ Timing (When DMD = 1 and DPOL = 0)........................................... 414

Figure 15.11 HIFDREQ Timing (When DMD = 1 and DPOL = 1)........................................... 415

Figure 15.12 Image of High-Impedance Control of HIF Pins by HIFEBL Pin .......................... 419

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