HD6417618 datasheet(438/646 Pages) RENESAS

438 / 646 page

Section 15 Host Interface (HIF)

Rev. 6.00 Jun. 12, 2007 Page 406 of 610

REJ09B0131-0600

Bit

Bit Name

Initial

Value

R/W

Description

0/1

R/W

HIFRAM Access Exclusive Control

Controls accessing of HIFRAM by the on-chip CPU for

the HIFRAM bank selected by the BMD and BSEL bits

in HIFSCR as the bank allowed to be accessed by this

LSI.

0: The on-chip CPU can perform reading/writing of

HIFRAM.

1: When an HIFRAM read/write operation by the on-

chip CPU occurs, the CPU enters the wait state, and

execution of the instruction is halted until this bit is

cleared to 0.

When booted in non-HIF boot mode, the initial value of

this bit is 0.

When booted in HIF boot mode, the initial value of this

bit is 1. After an external device writes a boot program

to HIFRAM via the HIF, clearing this bit to 0 boots the

on-chip CPU from HIFRAM.

When 1 is written to this bit by an external device, H'A5

should be written to bits 7 to 0 to prevent erroneous

writing.

15.4.10

HIFDREQ Trigger Register (HIFDTR)

HIFDTR is a 32-bit register. Writing to HIFDTR by the on-chip CPU asserts the HIFDREQ pin.

HIFDTR cannot be accessed by an external device.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 1

—

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

HD6417618 Datasheet(PDF) 438 Page - Renesas Technology Corp

HD6417618 Datasheet(HTML) 438 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL